Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors

Mukherjee Chhandak (1, 2) , Guilhem Larrieu (3) , Cristell Maneux (2)

1 CNRS - Centre National de la Recherche Scientifique
2 IMS - Laboratoire de l'intégration, du matériau au système
3 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique

This paper presents a physics based, computationally efficient compact modeling approach for 3D vertical gate-all-around junctionless nanowire transistor (JLNT) arrays designed for future high performance computational logic circuit. The model features an explicit continuous analytical form adapted for a 14 nm channel JLNT technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary logic circuit simulations have been performed for benchmarking performances of transistor logic circuits, such as inverters and ring oscillators, designed using the developed model.

Mots clés: Junctionless nanowire tranistors; compact model; high-speed logic circuit; heterogeneous integration

Domaines: Electronique; Modélisation et simulation; Technologies Émergeantes [cs.ET]

Mukherjee Chhandak, Guilhem Larrieu, Cristell Maneux. Compact Modeling of 3D Vertical Junctionless Gate-all-around Silicon Nanowire Transistors. EuroSOI-ULIS 2020, Sep 2020, Caen, France. ⟨hal-02869216⟩